FIG. 18 shows a conventional conductive bridging random access memory (CBRAM) type memory element 1800, also sometimes called a programmable metallization cell (PMC). Memory element 1800 has a vertical stack, including a cathode 1803, an ion conducting layer 1805, an anode 1807, and a top contact 1809. A cathode 1803 can be formed in a first insulating layer 1811, and is made of an “inert” conductive material that does not ion conduct in ion conducting layer 1805.
An anode 1807 can be made of an “active” metal that ion conducts in ion conducting layer 1805. In the conventional example shown, an anode 1807 can be formed of silver (Ag).
Ion conducting layer 1805 can be formed between the anode 1807 and cathode 1803, contacting the cathode 1803 through an opening in second insulating layer 1813. By application of a bias voltage across anode 1807 and cathode 1803, a metal within anode 1807 can ion conduct within layer 1805 to thereby create (or dissolve) a conductive path (e.g., a filament). The presence of the conductive path can represent one data state (a low resistance state). The absence of the conductive path can represent another data state (a high resistance state). In the conventional example shown, ion conducting layer 1805 can be formed of the chalcogenide GeS2.
An anode 1807 can be biased to a voltage by way of top electrode 1809.
One possible drawback to a conventional memory element like that of FIG. 18 can be mechanical stresses that can arise during temperature changes. In particular, there can be a substantial difference between the thermal coefficient of expansion of the anode 1807 (i.e., silver) and other section of an integrated circuit (i.e., silicon). Accordingly, changes in temperature can impart mechanical stress on the device.
Another possible drawback of a conventional memory element like that of FIG. 18 can be the unconstrained movement of anode material. Upon dissolution of filaments, atoms making such filaments may not return uniformly to anode 1807.